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Re: [f-cpu] F-CPU vs. Itanium

> recently. When `loada' is executed, mark the corresponding bytes in the
> cache, and reset the markers whenever an instruction modifies the loaded
> data. If the markers aren't all set (or the cache line was flushed),
> the `verify' instruction will trap, jump to a piece of fixup code, or
> simply re-load the modified bytes. The drawback of this approach is that

nice :) the same like IA64 "advanced load" only doesn't need additional
associative memory. But see below.

> it doesn't work well if the same bytes are loaded more than once, or if
> the loaded register is overwritten. I'm not sure how the Itanium handles
> that case, however.

It does it like your register<->address map table. They have 8 entry
associative memory where each line holds address and register id.
load.a adds line with addr/reg (doing LRU on old entries). verify (it
has another name which I can't recall) looks for line with reg id.
Store deletes all lines with matching address.
It handles more-load case but not overwritten reg case. However there
is kind of verify instr which removes the entry IIRC.

> That's why ISO C99 adds the `restrict' pointer qualifier. E.g. you write
> [...]

ehh I should probably reread new C specs ;)


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