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Re: [f-cpu] Winograd DCT on my seul.org account

> Martin Devera wrote:
> > > However this creates a new kind of problems : gcc should export
> > > the whole Intermediate Representation instead of just register-wise
> > > code, because register reallocation works best on program-wise
> > > working sets. Usually, FPGA/ASIC synthesiser + fitter exchange data
> > > in the form of a flattened netlist, but GCC outputs code
> > > that almost looks like already-fitted code.

> > By the way there is already gcc3 patch which exports whole
> > IR as XML .. (http://sourceforge.net/projects/introspector/)

> that's a good news !

Hum,... If we use the IR XML representation, we can not represent much more 
than what the backend of gcc receive. So we will not be able to do a better 
work than a normal gcc backend, without the compatibiliti...

> > But then your postprocessor will be the same as "detached"
> > gcc backend IMHO.
> why not.
> but my initial idea was to give GCC an oversimplified ISA
> and do the naughty F-CPU stuff ourselves.
> Using XML would force me to learn it and GCC3 is not well percieved,
> but it's a bet on the far future.

XML, is only a way to see a tree, and gcc3 is actually far from a perfect 
compiler, but I think that he will be ready when we have a prototype. And at 
this time he will probably generate some SIMD code ;-)

> > devik
> > PS: have my Itanium question been so dumb or did I violated
> >     some f-cpu list roles ?
Of course not, but what can we say before we have a prototype, it's not really 
realistic to compare a virtual CPU even if we can imagin it, to a real one 
that intel will probably remove from the market (because of AMD x86-64).

But if you whant to know for the dnetc algorithm, I need 300 instructions per 
keys, and an estimation of AMD Athlon give me 250 cycles per keys...


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