Re: [f-cpu] Alternative ROP2 Implementation

[devik <devik@cdi.cz>]

it is for xc2s300e-pq208-6, thus the faster (bigger) one.

On Tue, 22 Apr 2003, Michael Riepe wrote:

> On Tue, Apr 22, 2003 at 01:20:54PM +0200, devik wrote:
> > > The fcpu-mr-rop2-20030421.tar.gz package (second attachment) contains a
> > > rewrite of the ROP2 unit that supports all instructions mentioned above,
> > > as well as combine mode up to a chunk size of 64 bits (but only for the
> > > ordinary logical operators, not for bitop -- I doubt that it makes sense
> > > for them).  Latency is critical in combine mode (I had to violate the
> > > 6G rule again, but I still obey the 10T rule), therefore I'd like to
> > > receive synthesis and speed reports.
> >
> > I have not older rop2 sources. Thus one uses
> > 556 slices and runs at 50.0 MHz.
>
> In the small or the bigger FPGA?
>
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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