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NB (Re: [f-cpu] Interim solution to prototype the core)



Dear everybody,

This is the summary of the last mail exchange on the list :

1 hour spent on pointless clichÃs.
1 subscriber fed up and left.
0 answer to my initial question.

This is the last time it happens and for the sake
of the project, our mailboxes and our sanity,
if I think that this is about to repeat,
I reserve the right to either remain silent,
use more sarcasm or take other necessary measures.

This is the 3rd time that the project is rebooted
and I will not let it crash and burn again.
At the same time, I don't want this list to be
a hostile environment, like lkml or worse.

We all want and long for actual results so let's think
constructively, about actions, instead of the "campfire"
spirit that failed so many times.
I start with myself by being more assertive.

Thank you for your understanding and please
accept my apologies for my sleep-deprivation-induced
grumpiness.

Le 2015-04-10 15:11, whygee@xxxxxxxxx a ÃcritÂ:
Le 2015-04-10 15:01, Nicolas Boulay a ÃcritÂ:
'+' or '*' or SRAM block it the same.

yes, sure.......

Beside that some synthetizer are scriptable, so you could guide the
synthese.

"some". and the next line you talk about universal rules.

If you optimise for a current FPGA,
the design will be obsolete when ready.

Thank you for your concern about the eventual
delivery of anything, one day.

yg

yg
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