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Re: [f-cpu] Re: FC0 XBAR
On Thu, Aug 02, 2001 at 08:31:06PM +0200, Yann Guidon wrote:
[...]
> > IMHO, reading and writing "in the same cycle" means that *by the end
> > of the cycle* (when the clock signal rises) the new data is stored in
> > the register, while the reader gets a copy of its *previous* contents
> > at the same time.
>
> that's what i feared :-(
I thought that's what the Xbar bypass is good for -- avoid the delay?
[...]
> Then there is another problem ! since the result is really written
> during the next cycle but available only the cycle aftern, people who
> want to optimise the instruction flow but who don't do it "perfetcly"
> are hit by a 1-cycle delay. Obviously, delaying is not a good thing :
> people will try to schedule the instructions close to the pipeline
> features, but there is a large chance that, under the pression of
> the program, available ressources and other stuff, the delay is reached.
Well, let's try an example to make this clearer. Let's say we want to
add 3 numbers:
add r5, r1, r2 ; temporary result in r5
add r4, r3, r5 ; final result in r4
Now, the time-table (without bypassing) is:
cycle 0: read r1 and r2 (pass values through Xbar)
cycle 1: stage 1 of ASU is working
cycle 2: stage 2 of ASU is working
cycle 3: pass result through Xbar (write r5 at end of cycle)
cycle 4: read r3 and r5 (pass values through Xbar)
cycle 5: stage 1 of ASU is working
cycle 6: stage 2 of ASU is working
cycle 7: pass result through Xbar (write r4 at end of cycle)
Note that r5 is written at the end of cycle 3, but read in cycle 4; that
is, the new value is read (and passes the Xbar again). With bypassing,
cycle 3 and 4 will overlap, resulting in a 1-cycle speed-up.
Or did I miss something?
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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