Re: [f-cpu] Register Bank

[Michael Riepe <michael@stud.uni-hannover.de>]

On Thu, Aug 02, 2001 at 10:09:11PM +0200, turlututu@bechamail.com wrote:
[...]
> 	Some vendors (ST micro, IBM, Atmel, ...) seem to dislike
> asynchronous resets in designs. They strongly prefer synchronous
> resets. Resets are managed in a unique module but we have to modify
> sequential processes; the original code is : 
[...]

> 	Note that the use of a constant for the reset value is the best way
> because you don\'t always know if the reset is active high or low before the
> choice of a vendor.
> 	Do not forget that a majority of vendors do not support tri-states
> ( \'Z\' ) in the core of a design, so we have to replace them with muxes.

This is only a case study, not the real code.

On the other hand, coding hints are welcome.  Thank you :)

> 	Could somebody tell me why there are
> \"Write_0, Write_1, Write_Enable_0, Write_Enable_1\"
> signals in the sensitivity list ?

Because some tools complain if they're not present.  I don't know why;
as far as I understood, only Clk is needed in a sequential circuit with
no asynchronous controls (which you just confirmed, somehow).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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