Re: [f-cpu] Register Bank

[Yann Guidon <whygee@f-cpu.org>]

hi,

Juergen Goeritz wrote:
> > Concerning the register set reset, it can probably be performed
> > with some "tricks" : "hard" reset is probably not necessary.
> > i think that a "smart" use of the scheduler can trigger a burst
> > of register writes after a reset. what do you think ? :-)
> 
> Depends on how long you can wait after reset. Some registers,
> e.g. of the internal pipeline statemachines have to be reset
> anyway. If you use 256 registers in some inplementation you
> would wait 256 clocks before the built-in selftest routines
> can start or you make the reset a part of these. :-)

given the 2 write ports, we have to wait during 32 cycles,
which is still decent, considering the much longer self-test
routines.

And if i'm not mistaken, there should be no scheduling or
priority problem because it uses the scheduler HW directly.

i'll have to include that in my C sims.

> JG
WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/