Re: [f-cpu] Register Bank

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Juergen Goeritz wrote:

> Typo! A latch will loose the information on a glitch, e.g.
> glitches in transparent select or data feedback mux control.
> It's hairy to use latches other than for input signal
> synchronization! I have been working 4 years in the
> field of PLD/FPGA as application engineer though. ;-)

I say latches have got a bum rap with FPGA's.Latches are harder
to use than F/F's as FPGA's routing makes timing calculations
very hard. FPGA's still can crap out with F/F's and route them
badly thus a design will not meet setup and hold times even
if your F/F's are something simple like n bit shift register.
Ben.
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
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