Re: [f-cpu] Register Bank

[Juergen Goeritz <goeritz@oekomm.de>]

On Tue, 7 Aug 2001, Yann Guidon wrote:
> > > basicly, the register set is split into 5 "banks" with individual
> > > write enables. what is even more difficult is how to handle the
> > > flags in parallel. The reason is that i have not practiced VHDL
> > > for a long time :-/
> > 
> > How comes that you use '5' banks? I remember the number of
> > registers to be 2^n even. 32/5 doesn't fit, 64/5 doesn't fit
> > either. I am a bit puzzled now. :?)
> 
> that's a "side effect" of using both partial writes for "normal"
> data and loadcons instructions :
>  the first one writes in 8, 16, 32 and 64-bit versions,
>  loadcons writes 16-bit data after a shift of 0, 16, 32, or 48 bits.
> The union of these fields gives :
>  0-7, 8-15, 16-31, 32-47, 48-63

Aha, a split in the width at different sizes. Interesting!

JG

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