Re: [f-cpu] Register Bank

[nicO <nicolas.boulay@ifrance.com>]

turlututu@bechamail.com a écrit :
> 
>                 Hello everybody,
> 
>         First of all, a little introduction :
> my name is Stéphane Bersin; I am an ASIC designer
> and I\'ve been working in telecommunications design center
> on GSM and UMTS for 4 years now.
> 
>         I read some of the posts of the f-cpu list, but I have
> too few time to participate to your technical exchanges. 8-(
> 
>         I read this afternoon a post from Michael Riepe with
> the regbank.vhdl file attached and I would like to make a
> technical add. I had to change my vhdl code ( in my current project )
> two months ago in order to comply with ASIC vendors .
>         Some vendors (ST micro, IBM, Atmel, ...) seem to dislike
> asynchronous resets in designs. They strongly prefer synchronous
> resets. Resets are managed in a unique module but we have to modify
> sequential processes; the original code is :
> 

I have read it in Synopsys recommendation. So it's better a 'feature' of
dc_compiler...

nicO
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