Re: [f-cpu] Re: Floating-Point?

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:
> On Tue, Aug 14, 2001 at 03:25:04PM +0200, Yann Guidon wrote:
> > hi !
> >
> > Juergen Goeritz wrote:
> > > On Mon, 13 Aug 2001, Yann Guidon wrote:
> > > > > do you have a link to basic floating point implementations
> > > > > that can be used to begin with a pipeline fpu unit?
> > > >
> > > > There are some docs floating around on Internet but nothing
> > > > that could do the trick for the FC0 (due to its specific structure).
> > > > superpipeline + SIMD is not easy to do.
> 
> SIMD is IMHO not reasonable for the FP units.
in what context are you speaking ?
SSE2, when correctly used, can do some nice things (if you don't
fall in Intel's crappy traps).

> A reasonable approach is
> to build a set of pipelined 64-bit FP units, and then issue the 32-bit
> operations in two consecutive cycles.
that's vectoring, then. Scheduling might become more complex,
in situations such as chaining for example.

I have nothing to object to that, but
 - 1) currently we have no FP unit
 - 2) SIMD already works well (when it does)
 - 3) vectoring will be used in another core because FC0 would require too much changes
 - 4) if you have 1 FP unit, the hardest is done : you can duplicate it :-P

> BTW: I think we need another instruction that converts 32-bit FP to 64-bit
> and vice versa (and maybe also does the mix/expand/sdup thingy for FP).

geez, the instruction set in the current version of the manual needs a big rework...

Sure, there needs to be an expansion/reduction code for FP
but SDUP works for SIMD FP if the packets have the same boundaries.

> While we're at it: something that I miss in most CPUs is `variable'
> register addressing, that is, accessing a register when its number
> is not known at compile time -- like get and put in the F-CPU, but for
> ordinary registers.  I know that this is likely to cause trouble with the
> scheduler, but what about mirroring the general registers in the SR area
> and simply use get and put?

that is certainly one solution. we've already thought about that, "long ago"
(if i can even remember), for register save backup/restore with a simple loop
(otherwise it would require 64 instructions min.).

however, it is not going to be easy in FC0 because the R7 read address ports
are directly connected to the instruction coming from the fetcher.

There might be a "dirty hacking solution" : the BIST needs to access the
three register read address ports in order to test the register set.
of course it's not going to be fast and clean, but it could work.


BTW i'm currently updating the ALPHAvsFCPU text.
it's getting larger and larger...

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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