Re: [f-cpu] Re: Floating-Point?

[nicO <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
> 
> On Tue, Aug 14, 2001 at 03:25:04PM +0200, Yann Guidon wrote:
> > hi !
> >
> > Juergen Goeritz wrote:
> > > On Mon, 13 Aug 2001, Yann Guidon wrote:
> > > > > do you have a link to basic floating point implementations
> > > > > that can be used to begin with a pipeline fpu unit?
> > > >
> > > > There are some docs floating around on Internet but nothing
> > > > that could do the trick for the FC0 (due to its specific structure).
> > > > superpipeline + SIMD is not easy to do.
> 
> SIMD is IMHO not reasonable for the FP units.  A reasonable approach is
> to build a set of pipelined 64-bit FP units, and then issue the 32-bit
> operations in two consecutive cycles.
> 

It's a kite big area but we need it.

> BTW: I think we need another instruction that converts 32-bit FP to 64-bit
> and vice versa (and maybe also does the mix/expand/sdup thingy for FP).
>

In sparc, there is no 80 bits float but 128 bits (2 registers used in
the same time). We don't need 1 cycle multiplication so it could be done
for the fcpu.
 
> While we're at it: something that I miss in most CPUs is `variable'
> register addressing, that is, accessing a register when its number
> is not known at compile time -- like get and put in the F-CPU, but for
> ordinary registers.  I know that this is likely to cause trouble with the
> scheduler, but what about mirroring the general registers in the SR area
> and simply use get and put?
>

This kind of readressing register is a little bit like memory adressing
for DSP. Register just contain address. But it's the same thing that
using memory, it make a much longer pipeline, it's hard to manage for
switching context,...

nicO
 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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