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Re: [f-cpu] Re: Floating-Point?



On Thu, Aug 16, 2001 at 01:49:27PM +0800, Glenn Alexander wrote:
> Hi. This is my first post to this list. My background is as a hardware 
> technician, not a chip designer so bear with me.
> 
> On Thursday 16 August 2001 03:41, you wrote:
> > Michael Riepe a écrit :
> > 
> > In sparc, there is no 80 bits float but 128 bits (2 registers used in
> > the same time). We don't need 1 cycle multiplication so it could be done
> > for the fcpu.
>   
> I am thinking that taking the two-register approach might be 
> over-complicating matters. Since F-CPU is intended to later be scaled above 
> 64 bits, if someone wanted 128-bit floats in the future they would impliment 
> a 128-bit F-CPU. Especially for the FC-0 and probably for the FC-1, KISS 
> (Keep It Simple for us Stupid people).

128-bit `quadruple precision' (like SPARC) is IMHO the way to go, but
not in the FC0.  For now, let's stick to 32-bit and 64-bit (with 80-bit
`double extended' used inside the FP unit, to maintain IEEE compliance).

> BTW: I am wondering about the reasons for having endian-ness encoded in the 
> instruction. How often do you need to change endinianness. I am thinking a SR 
> for endinian would free up that bit as well as allowing other endiniannesses 
> as well as big and little (Not in popular usage at present but I can think of 
> several other bizaar ways to re-arrange the bits in a word that may be useful 
> in some obscure application).

Please don't.  Mode registers are a PITA.  You never know whether
they're set correctly (like the `D' flag on x86).  Except for the
register width translation SRs, NO special register should affect
the semantics of a program!

We could drop the `e' flag and use [s]byterev.* to swap the bytes.
But byterev takes 3 extra cycles to execute, while load/store don't slow
down in `foreign-endian' mode.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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