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Re: [f-cpu] the wrong way (of floating point and so on)



hi,

Ben Franchuk wrote:
> > I think we should forget to trace the way to include floating point now.
> > Why?
> > IMHO there are too many tasks to do, which are more important than
> > thinking about floating point units. First, we should have a working
> > "simple" F-CPU, not more nor less.
i agree.

> > Second, a FPU was declared as an optionally unit,
> > Floating-point-operations are rare and should be emulated in an
> > intelligent way (software) to use the full power of F-CPU's
> > SIMD-capabilities
> > Last, If we are better in designing units and we have a real (!) F-CPU we
> > can easily extend the core with an existing FPU, I think.
that's the idea, yes :-)

> > In my mind I do not realisize how you will design the scoreboard and the
> > shifting unit in a possible way or I misunderstood anything.
i am working on the scheduling issues. I leave the shifting unit
for whoever wants to have some headaches :-)

> > In my opinion we need in near future a working CPU to get and hold a good
> > developer-basis, and to make tests in reality not in emulations only.
at least, emulation is not expensive ;-)

> > Because we can compose a set of FPGAs (Altera and Co.) to load and emulate
> > the CPU, we should go in this direction, to make FC0 to that what it is,
> > "a proof of concept".
> >
> > I am in right?
at least it's not too far.

> I suspect it better to design for the floating point unit now
> but leave it out when on the first revision of the cpu design.
> Otherwise you could have a large problem trying to "patch" the
> floating point unit to the cpu. Say for example you wanted a few
> extra bits used just by floating registers you may use 67 bits
> for all the registers?This could have a large impact if you all
> ready designed 64 bit registers.
not necessarily.
When "customizing" the F-CPU design files, the user has to
indicate which units he wants implemented. The files go through
m4 and generate other files which can implement conditional compilation, too.

This means that "if it is well done", we can avoid problems in the vein that
what you have described : the bits will only be implemented if the
necessary flags or features are required. Ain't conditional compilation cool ? :-)

> Ben.
> PS. I suspect using low cost (slow) Altera parts you will have a
> clock rate about 8-16 Mhz.
even that is far too fast :-P

OTOH according to some figures given by nicolas, a FC0 ASIC could
reach 400MHz in .18u.


nicO wrote: (about FPU)
> An other trick could be used : It's to implement the full set of
> instruction but when a none present instruction is decoded a specific
> execption is raised and a specific code is runned. This code could be a
> part of the fcpu and not from a compiler. So you keep the complete
> compatibility. That's what has been proposed a long time ago.
> 
> nicO

yep, that is probably going to happen, as soon as we have a working
"execution core" for the FC0. notice that the "valid instructions"
depend on whether the corresponding unit is present/implemented or
not. We could provide some sort of "microcode" (in fact : a hardwired
and optimised emulation routine in F-CPU binary format) directly in the VHDL
source, and it will be selected/switched with the user configuration file.


WHYGEE
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