[Fwd: [f-cpu] the wrong way (of floating point and so on)]

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Yann Guidon wrote:
> This means that "if it is well done", we can avoid problems in the vein that
> what you have described : the bits will only be implemented if the
> necessary flags or features are required. Ain't conditional compilation cool ? :-)

How high level will the tools be? A adder could be a stock adder
or custom designed
one at the transistor level? Ripple carry? Carry lookahead?
Carry-skip?
 
> > Ben.
> > PS. I suspect using low cost (slow) Altera parts you will have a
> > clock rate about 8-16 Mhz.
> even that is far too fast :-P
> 
> OTOH according to some figures given by nicolas, a FC0 ASIC could
> reach 400MHz in .18u.

Did you know intel is claming a 2 GHZ chip? Still 400 MHZ is not
to shabby.
 
 
> nicO wrote: (about FPU)
> > An other trick could be used : It's to implement the full set of
> > instruction but when a none present instruction is decoded a specific
> > execption is raised and a specific code is runned. This code could be a
> > part of the fcpu and not from a compiler. So you keep the complete
> > compatibility. That's what has been proposed a long time ago.
> >
> > nicO
> 
> yep, that is probably going to happen, as soon as we have a working
> "execution core" for the FC0. notice that the "valid instructions"
> depend on whether the corresponding unit is present/implemented or
> not. We could provide some sort of "microcode" (in fact : a hardwired
> and optimised emulation routine in F-CPU binary format) directly in the VHDL
> source, and it will be selected/switched with the user configuration file.

I like a separate math floating point FPGA idea like intel did
with their CPU's.
  
> WHYGEE
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Ben.
PS. Yipes supper is burn...
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
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