|
Ben--
I will be using QL6600's of the Eclipse Family from
Quicklogic having 4032 Logic Cells.
The Language Processor uses two FPGA's and the
Peripheral Processor is a mirror image.
Each ERIN32 consists of a Data Processor & an
Address Processor. I fetch four instructions and four operands in
parallel. The Microinstruction is 72 Bits, where 18 are Source address and
18 Bits are Destination address. Modified Harvard
Architecture.
The instruction Pipeline is four deep. And
where possible all four are executed. I have a Bit in the instruction
which I call DDP (data dependent) if an instruction requires the result of the
previous, I have a controlled stall/restart.
There seems to be a direct correlation of
performance to pipeline depth. I.E.--
1, 2, 4, 8.16 etc. I will have a 200 MHZ
average execution time operating from a base 50 MHZ oscillator applied to a
PLL.
The design is NOT logic cell limited. The DAP
uses 2100 cells and the ADP uses 1800 - most are used by Multiply and Divide
instructions. I was going to have these as optional instructions - but since I
had space to burn, they are free-bees.
I am using Synchronous Static Rams (SSRAM) from
Cypress Semi. Both two port and four port. The local memory is essentially
an Orthogonal Array. Access time is 4.5 NS for both types.
I am currently doing the FBC (fully buffered
channel) which should be complete this week. Will probably use an QL6500
here.
Next I will be doing the CICU (Console Interrupt
Control Unit) for 128 User Stations.
This design should take two weeks - and at this
point I will have all designs completed for the Expo at San Jose.
Don't hesitate sending Questions - the only thing I
have that is Company Private is the Memory Architecture.
Regards
Dick Hartney
|