Rep:Re: Rep:Re: Rep:Re: [f-cpu] TLB resume

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: Michael Riepe <michael@stud.uni-hannover.de>
A: f-cpu@seul.org
Date: 12/08/02
Objet: Re: Rep:Re: Rep:Re: [f-cpu] TLB resume

On Sun, Aug 11, 2002 at 06:29:45AM +0200, Yann Guidon wrote:
[...]
> The idea here is that one could read the "hidden flags"
> associated to a pointer/register. When it comes to the other
> flags (MSB, Zero etc) they are implicitly available through
> the conditional instructions. I don't think it's overly complex
> to do a "pointer test" instruction because load and store are
> also conditional instructions, though more complex :
>  - is the register marked as a pointer
>  - is it valid
>  - is the associated data present
>  - what access rights are granted (R,W,RW or X) to current process.

That could be a security risk if the instruction is not privileged.

>>>If a program could verify the protection of his pages, you couldn't
virtualise a task any more.

> Here are what these flags indicate :
> 
> * if the register is not marked as pointer, a load/store/jump
> will perform some synching cycles (pass the register value
> through TLB then compare the address with the LSU/Fetcher entries.
> * if it is not valid, any access (load/store/jump) will trigger
> a trap.

Does `not valid' mean that the register's value is currently being
computed?

> * if the data is present, the load/store/jump instruction will
> not stall.
> * if the access right is
>   R -> store and jump will trap (protection error)
>   W -> load and jump will trap
>   RW-> jump will trap
>   X -> load and store will trap

Executable pages usually are readable, too. They may contain read-only
data (string constants), jump tables and so on.

>>> So for that kind of pages set the r bits, or put all this stuff in a
specific pages (i prefer this solution). R that imply X is the killing
problem of x86.
nicO

> Note : in FC0, aliases between the LSU and the fetcher give
> potentially wrong results -> the presence must be exclusive,
> or the whole system breaks. but i presume nobody will make
> self-modifying code, right ? So we can spare 1 bit and encode
> the allowed rights in 2 bits only. The same remark also
> applies to the TLB entries. OOOPs, i shouldn't have
> written that... it'll trigger a lot of mails again
> and i was quietly programming some useful software :-)

Dynamic linking usually requires that code pages can be modified at
runtime (the PLT is maintained that way).  When demand paging is used,
it's also common that a page is written to immediately before it is
executed.  In either case, the LSU and the fetcher will have to
cooperate.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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