[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Conditionnal load and store, the return



> > > load the data ? what data ? the conditional load only to need access
> > > to memory if condition is true, so even an exception occurs, when
> > > reexecuting the faulty instruction, all is okay. Same thing for the
> > > conditional store.
> > > So i don't see any problem.
> >
> > You will not reexecute it. I mean the conditionnal store on wich we
> > discuss test if the condition register is zero or not, or if the lsb/msb
> > if zero or not and if the test is true, the write is done. If you load
> > a data conditionnaly, if the address isn't ok, and the test is false, no
> > exeption must occur and it's where the problem is.

> 'load' : you mean you always load the value from memory and assign the
> value to the data register only if test is succeeded ? well, if so, an
> exception will occur before any test anyway. But you still must reexecute. 
> Page fault exception must point on the faulty instruction and must resume 
> the faulty instruction since we suppose we've just resolved the fault, so
> the program can continue as if there was no fault. It is the behavior you 
> will find on all CPU for mmu management. Otherwise, you wouldn't be able to
> virtualize memory.
 
> But if you only access memory just after the test succeeds, an
> exception will occur and still you need to rexecute the instruction.

And what append if you point to NULL and the test is false ? You can't
reexecute it and never. So what did you do ?

Cedric
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/