[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: [f-cpu] F-CPU architecture...

Yann Guidon wrote:
Michael Riepe wrote:
ROM is probably useless.

I know you know this but let me state a few things nevertheless.

First reason : FC0 will certainly "live" as a FPGA in the beginning,
so no need to make exhaustive failure verification.

Do not skip testability issues just because your prototype stage will be FPGA! The LEON made this mistake and was hard to port to ASIC!

Second reason : i had found, years ago, how to create the BIST
using a FMS (some hundred thousand cycles are enough, the key
is to find in which order to send signals through the pipeline).

My collegue develops a technique to test a processor via a Software Based Self Test that yields very high fault coverages at low power and short test times.

It will be general enough to apply to F-CPU in about a year. She's currently working with a simple RISC and the LEON2.

Third reason : RAM is better and cheaper.
And I think that bootstrapping the CPU with the help of an external,
cheap microcontroller is a good help.

I'm even thinking about putting a simple RISC like a LEON on die as well and let it handle the I/O and selftest. If done it switches to I/O pass through mode :)
And don't tell me: "OMG. So much die space wasted!" If F-CPU is to be high end then the size of a wasted LEON is almost 0 in comparison!

bis besser,
To unsubscribe, send an e-mail to majordomo@xxxxxxxx with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/