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Re: [f-cpu] F-CPU architecture...

Hi F-gang,

Tobias Bergmann wrote:

My collegue develops a technique to test a processor via a Software Based Self Test that yields very high fault coverages at low power and short test times.

Sounds interesting. How does that work, approximately?

It will be general enough to apply to F-CPU in about a year.

That's probably not too late ;-)

I'm even thinking about putting a simple RISC like a LEON on die as well and let it handle the I/O and selftest. If done it switches to I/O pass through mode :)

Well, the I/O thing is still more or less undesigned anyway. We had plans for the "G" (as in "glue") chip which is a kind of crossbar switch supporting three or four F-CPUs and maybe also including some I/O devices. It could be used to distribute boot code to the CPUs, too.

The basic idea is that the F-CPU contains a DMA engine that transfers data from I/O to memory and vice versa. When the chip is reset, the engine would be preset to receive a fixed amount of data from the I/O bus and transfer it to a fixed physical address (most likely zero) where the F-CPU can execute it.

And don't tell me: "OMG. So much die space wasted!" If F-CPU is to be high end then the size of a wasted LEON is almost 0 in comparison!

I'd rather use a downscaled version of the F-CPU itself. Maybe even the mythical 32-bit version that some people already have asked for, with all the unnecessary stuff stripped off (e.g. FPU, multiplication and division).

Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
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