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Re: [f-cpu] F-CPU architecture...

Michael Riepe wrote:

I'm even thinking about putting a simple RISC like a LEON on die as well and let it handle the I/O and selftest. If done it switches to I/O pass through mode :)

Well, the I/O thing is still more or less undesigned anyway. We had plans for the "G" (as in "glue") chip which is a kind of crossbar switch supporting three or four F-CPUs and maybe also including some I/O devices. It could be used to distribute boot code to the CPUs, too.

With the advent of a new organisation (with FC0 having one specific I/O channel),
the "G chip" can be a simple FPGA. This makes it much more cost-effective and practical :
some FPGAs can be had with a thousand pins, expensive but much less
than if we designed our own G-chip with as many pins. And we can develop
the routing algorithms, etc, without having to going to fundry.

The basic idea is that the F-CPU contains a DMA engine that transfers data from I/O to memory and vice versa. When the chip is reset, the engine would be preset to receive a fixed amount of data from the I/O bus and transfer it to a fixed physical address (most likely zero) where the F-CPU can execute it.

That, or a simpler way : init PC=0, which triggers cache fault, (because RESET has flushed everything) so reads from outside memory (private memory is not mapped to address 0) ---> no need to design the DMA specificically for booting.

And don't tell me: "OMG. So much die space wasted!" If F-CPU is to be high end then the size of a wasted LEON is almost 0 in comparison!

I'd rather use a downscaled version of the F-CPU itself. Maybe even the mythical 32-bit version that some people already have asked for, with all the unnecessary stuff stripped off (e.g. FPU, multiplication and division).

If the "scaled-down core" is never going to run applications or user code, then use the VSP :-P


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