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Re: CRC (was Re: [f-cpu] F-CPU architecture...)

that contains about 1500 2-input xor gates (rough estimates from memory). 6 levels of xor gates is about 6*70ps at 0.13u, add some wire delay and you still get quite respectable speed :) And CRC calculation can be pipelined if needed, but that is little more difficult. The single cycle xor-network is quite trivial and well known in the literature.

thank you for the info !

and how would this work with wider data ? like 128 and 256 bits wide ?

I finally found the webtool to calculate these things:


You can check yourself :) If you are an ieee member http://intl.ieeexplore.ieee.org/xpl/abs_free.jsp?arNumber=623934 tells more about the technique. There are also many tools with source code in the net, for example in the xilinx appnotes.

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