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[f-cpu] F-cpu pipeline
- To: <f-cpu@seul.org>
- Subject: [f-cpu] F-cpu pipeline
- From: <nicolas.boulay@ifrance.com>
- Date: Tue, 11 Dec 2001 12:09:43 GMT
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- Delivered-To: f-cpu@seul.org
- Delivery-Date: Tue, 11 Dec 2001 07:09:53 -0500
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It's a paper about the next generation AMD cpu.
I suggest you to analyse the pipe. 32 stage !!!
But always only one for ALU/execute stage. I know
that FCPU is much simpler but it's hard to imagine to
have à 100 stage cpu...
(look at 7 fetch stages divide in 2 fetch and 2
decode compare to 1 execute)
I don't say to stop making the fcpu as it was said
but we shoud be more flexible for the design of the
scheduler.
Have a nice read !
nicO
http://www.amd.com/us-en/assets/content_type/Download
ableAssets/MPF_Hammer_Presentation.PDF
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