Re: [f-cpu] FC0's RTL scheduler

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:
> On Tue, Dec 18, 2001 at 03:31:02PM +0100, Yann Guidon wrote:
> 
> > > > I see that we have most EUs going on or done
> > > > so this is the best place to work. However i still
> > > > have to figure how many output ports the IMU has.
> > > Eight -- two for each chunk size (holding the high and low parts of
> > > the double-width product). We have to reorder the result bits for the
> > > original macl/mach instructions, however.
> > can you be more precise ?
> >
> > does that mean that :
> >  8-bits   -> 2 cycles
> >  16-bits  -> 4 cycles
> >  32-bits  -> 6 cycles
> >  64-bits  -> 8 cycles
> > plus an additional cycle for mach/macl ?
> 
>          8-bit low  part -> 3 cycles
>          8-bit high part -> 4 cycles
>         16-bit low  part -> 4 cycles
>         16-bit high part -> 5 cycles
>         32-bit low  part -> 5 cycles
>         32-bit high part -> 5 cycles
>         64-bit low  part -> 6 cycles
>         64-bit high part -> 6 cycles
> 
> mach/macl work at the same speed, but the results don't appear at
> the bit positions that are documented in the manual. In the manual,
> there is a difference between mul and mac modes -- mul(h) places the
> high part of every result chunk in the secondary destination register,
> while mac[lh] pastes high and low parts together, doubling the chunk
> size of the result, and then selects one half of the result and puts it
> into the primary destination register (the secondary reg is never used).
> The final chunk-shuffling for mach/macl is currently not implemented
> (it can be handled by adding extra output ports for mach/macl, or by
> reordering the chunks in the Xbar, whichever is cheaper).

maybe we can "cheat" with the scheduler : swap the register number,
instead of the data, and validate one or another ? it can save one cycle
at the "cost" of missing some issue opportunities but they can be recovered
with a careful coding uideline. what do you think ?

And can you explain a bit how the output ports work ?
how many do you need ? And what about the normal operations ?
(mul) I'm currently too lazy to read all your code, i hope
you understand ;-)


>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PS: big thank to Josh for his recent synthesis run !
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/