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[f-cpu] EU precision, use of Q1,Q2,Q4, number inside the core



An idea	come to me few days ago. I hope it's not too late. I have
followed a little the ffmpeg development : it's video compressor suite.

The 40% of the time is taken inside a IDCT routine in mmx ASM. They were
a flame war because the current IDCT have rounding problem and the image
goes darker. An other routine as been written but was slower.

My idea is to do as DSP do : create register with more bit than
expected. For example, we could use 1 bit more for 8 bit operation, so 2
for 16 bit (signal processing), 4 in 32 bits. Its became Q1, Q2 and Q4
numbers. During write to memory there are dismiss.

Comments ?
nicO

Yann Guidon a écrit :
> 
> hi !
> 
> Michael Riepe wrote:
> > On Sat, Dec 22, 2001 at 04:08:44AM +0100, Yann Guidon wrote:
> <snip>
> > > In the scheduler FIFO, i have two columns of N positions
> > > (N-deep FIFO) with each the following informations :
> > >   - valid           (1 bit)
> > >   - register number (6 bits)      -> used during the register write cycle
> > >   - write mask      (2 bits)      -> used during the register write cycle
> > >   - write port      (3 or 4 bits) -> used during the Xbar cycle to select the data
> > > Each FIFO stage contains (for most bits) a register (that is clocked
> > > by the main clock), a few comparators (for the register numbers)
> > > and a MUX that selects either the previous stage's data OR the data coming
> > > from the decoder's LUT.
> <snip>
> > It's crystal clear :)  And it looks good to me.  I would probably
> > store a pre-decoded write mask (5 bits) instead, but that's a minor
> > issue.
> it is minor, and in fact only 2 bits are necessary.
> the other bits are added at the bottom of the FIFO because
> no "regular" operation writes to a specific 16-bit chunk.
> The added bits are needed _only_ for the loadimm instructions,
> which do not need to go through all the FIFO (they take only 2 cycles).
> 
> <snip>
> 
> WHYGEE
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