Re: Re: [f-cpu] GCC 3.1 for F-CPU port

[devik <devik@cdi.cz>]

> > 1 cycle latency (it is regular EU, not as move or loadcons whose
> > emits value directly from decode FFs to xbar). Because gcc currently
> > can't schedule across basic blocks it often stalls at next insn after
> > widen.
>
> I am perhaps wrong but I think that bypass solve this problem (In fact if we
> have a loadconsx, I think that it will use the same EU as widen). And in fact
> a latency of one is like having the result ready for next instruction. Is it
> true, Yann ?
loadcons
widen
add
 sequence with the same reg:

xbar_in    xbar_out BSU_input BSU_output  decoder_out_insn
c                                         loadcons c
           c        c                     widen
wc                             wc         (stall)
           wc(bypass)                     add

So that there will be stall (almost surely).
When I hacked on GCC I found that it can happily live without
loadcons insn. It uses memory load instead. What about to drop
loadcons.N entirely and define:

loadcons s18,r

to load signed 18bit constant (bit17 is simply duplicated
over whole SR_MAX_SIZE). No partial writes anymore. You
can load majority of needed small constans and large ones
can be loaded from memory table indexed by smaller constant.
There would be register for it (like got, plt ...) which
doesn't need to be global. It can be loaded in function
prolog by substracting small constant from PC (loadaddrdi).
Like:
c1: d64 0xff4fffffff77878ff
c2: d32 0x12341234
f:  loadaddrdi -16,t0
    .. push frame here ..
    loadi.64 8,t0,t1  ; load c1
    add.64 a0,t1,t2
    loadi.32 4,t0,t1  ; load c2
    mul.64 t2,t1,t1

In fact when properly scheduled it can be even faster than
bunch of loadcons.N (with shorter code). Loading from ICACHE
would be better but ....
GCC could also alias more equal constants into one giving
more compact code.

Just another idea ...
devik

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