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Rep:Re: Rep:Re: [f-cpu] signed cmpl
- To: <f-cpu@seul.org>
- Subject: Rep:Re: Rep:Re: [f-cpu] signed cmpl
- From: "Nicolas Boulay" <nicolas.boulay@ifrance.com>
- Date: Wed, 18 Dec 2002 09:45:05 GMT
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- Delivery-date: Wed, 18 Dec 2002 04:45:24 -0500
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-----Message d'origine-----
De: Michael Riepe <michael@stud.uni-hannover.de>
A: f-cpu@seul.org
Date: 18/12/02
Objet: Re: Rep:Re: [f-cpu] signed cmpl
On Wed, Dec 18, 2002 at 11:52:37PM +0100, nico wrote:
> > > I had proposed a long time ago, to use the 6 bits register adresse
> > > field to create an immediat adressing mode available for every
> > > instructions.
> >
> > With the constant following in the next 32-bit word(s)? Well, no.
> > I don't want to build yet another CISC machine.
>
> ??? i never proposed that. Juste to use 6 bits of the field. Nothing
> more easy to do in hardware.
Sorry, I misunderstood. But on the other hand, 6 bits aren't much for
most purposes - you would have to `loadcons*' more often...
>>>Only our gcc expert could answer. So, does 32 to -32 number (or 0 to
64) immediat instruction could cover most immediat instructions used by
gcc ?
nicO
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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