[f-cpu] back to VHDL

[Yann Guidon <whygee@f-cpu.org>]

Hello !

I just finished one of the building blocks of the register set,
namely a "slice" (8 or 16-b wide) of 63 registers. It is a generic
stuff that now simulates correclty. I also updated my "stable" tree
with Michael's modified version of "fanout_linear" that works
with Vanilla.

I have one question however : Can we "link" the SHL unit to the
LSU ? This would allow us to perform both endian and alignment
with few overhead and some flexibility : it would even allow
us to do "signed" loads, where the data is first aligned and
then sign-extended... This is often used for CPUs like ALPHA
and MIPS where data are handled only in a word-sized way.

what do people think ?

WHYGEE
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