Re: [f-cpu] register set

[Kim Enkovaara <embo@mpoli.fi>]

> I have based the design on transparent latches,
> they ensure that the cells are not too large and slow.
> It's almost completely asynchronous : reading is just
> combinational (the address is driven by the fetcher's

Have you tought about test structures for ASIC manufacturing? Latches are
never fun thing to test. D-flipflops are so much easier to test with
normal scan paths.

--Kim

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