Re: [f-cpu] register set

[Juergen Goeritz <goeritz@oekomm.de>]

On Tue, 12 Feb 2002, Ben Franchuk wrote:
> Juergen Goeritz wrote:
> > > And on the philosophical point of view I agree with you but on the
> > > practical point of view, do you really want to redesign basics blocs
> > > such RAM, filebuffer ??? Do you really want to redesign the whole
> > > library ?
> > 
> > God beware! No, that wasn't the point. The point is to extract
> > basic macro functions out of the behavioural design to save
> > both space and layout cost (and delay time of course). And to
> > give backannotation hints to the designer which specialities of
> > his design prevent from using them. This would give more freedom
> > to the designers.
> 
> I see all HDL as F**King useless as being portable and free because
> 1) Hardware feature sets are not portable like FPGA's. Brand X has dual
> port ram , Brand A has block ram
> 2) Useful operations like addition with carry in,out and overflow are
> not supported in the language. You end up reinventing the wheel.
> 3) The source luke ... use the source ... what source for the libraries?
> 4) You still have to have two versions of source, 1 for simulation and 1
> for real gates. Easy to get them out of sync.
> 5) Hard to get at real transistors!

Yes, that's what I see all the time. Changing vendors isn't
really easy. There is a need to define an own process down
to the layout of cells or transistors. Simulation has to be
consistent on all levels. And I rather want to simulate the
software too before I go for silicon.

> > But on the other hand this may also be an indication that a lot
> > of the design already gets lost when you write it down in VHDL,
> > i.e. translation from mind to VHDL to compiler to gates/cells.
> > 
> > Sometimes it's a pity that one is forced to an implementation
> > already in the early stages of a design.
> 
> I think a RTL style language is best, not vhdl or verlog. Mind you the
> last nice RTL language I saw was for punched cards computer and output
> to FORTRAN as simulation.
> (A yellow book if I remember right with a title like  Register transfer
> language  and simulation ) 

I worked a lot with table driven input languages. Contrary to
VHDL you see at the first view how the signals behave. With VHDL
you first have to activate your inner interpreter to analyse the
code before you have the essence. With tables you take one look
and you have the essence. With tables the outputs are not hidden
behind a program structure.

That's what I think of being the most disadvantage of VHDL. You
write a program to create a table that the optimizer must extract
from the written code. The complexity does not lead to best results.
It's like writing all your email using SMS on a wireless phone.
Which means one has to concentrate on the input process and hardly
the contence.

JG

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