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Re: [f-cpu] register set



hello,

i did not step into this discussion mainly because of lack of time.
And also because i don't have the intention to argue (everybody has
a point), i simply search a way to design a portable register set
in VHDL.

Fortunately, VHDL provides a way to decouple the interface
from the implementation : the "entity" and the "architectures"
so when someone targets a specific technology, he adds a new
architecture and respects the interface that was defined
in the "entity". If his technology provides a 1-to-1 mapping
of the desired function : fine :-) otherwise, a certain amount
of code is necessary to "wrap" the physical entity.

Ben Franchuk wrote:
> Juergen Goeritz wrote:
> > > And on the philosophical point of view I agree with you but on the
> > > practical point of view, do you really want to redesign basics blocs
> > > such RAM, filebuffer ??? Do you really want to redesign the whole
> > > library ?

it didn't take long to write the 3R2W buffers, btw.
but it's only a "behavioural" description.

> > God beware! No, that wasn't the point. The point is to extract
> > basic macro functions out of the behavioural design to save
> > both space and layout cost (and delay time of course). And to
> > give backannotation hints to the designer which specialities of
> > his design prevent from using them. This would give more freedom
> > to the designers.
> 
> I see all HDL as F**King useless as being portable and free because
> 1) Hardware feature sets are not portable like FPGA's. Brand X has dual
> port ram , Brand A has block ram
that's why VHDL is used : to hide these implementation details.
whether bad or good, i won't argue. Concerning F-CPU which is to be
retargetable, it is a nice thing.

Currently there is no target technology, so we can write our code freely
and concentrate on the function and behaviour rather than focusing
on performance right now. It's like writing in C : i hate it but it's
used almost everywhere (except that i don't hate VHDL and VHDL is
not a widespread langage, but it's another troll ;-D).

> 2) Useful operations like addition with carry in,out and overflow are
> not supported in the language. You end up reinventing the wheel.
i agree with you here. but you know, "design by committee"...
like here, they have to stop talking before they can do things,
and then maybe they are good.

> 3) The source luke ... use the source ... what source for the libraries?
what do you mean by libraries ? btw, we use only IEEE libraries.
When we need something else, we write a new package that holds the F-CPU copyright.

> 4) You still have to have two versions of source, 1 for simulation and 1
> for real gates. Easy to get them out of sync.
in theory yes. In practice, the "behavioural" rules over the "real gates"
and the "entity" files do not change often.

> 5) Hard to get at real transistors!
yup, but in reality, if you get that low, you end up stuck with a fab house :-(
F-CPU, for those who don't know (there are newbies here) is about freedom,
so being restricted to only one fab is not good, and would render our
work useless when the process evolves. And it's not only about geometric
design rules ! 6 months ago, i would still have designed logic gates using
several pass transistors... But today's rules have to deal with ultra-low
voltages and pass transistors are much more restricted.

> > But on the other hand this may also be an indication that a lot
> > of the design already gets lost when you write it down in VHDL,
> > i.e. translation from mind to VHDL to compiler to gates/cells.
Fortunately, unlike C or other langages, VHDL provides a lot of
levels of description.

> > Sometimes it's a pity that one is forced to an implementation
> > already in the early stages of a design.
> I think a RTL style language is best, not vhdl or verlog.
I agrgee on one side but this creates new problems when dealing with
multiple targets with different architectures and granularities...
imagine FPGA1 with 3-input gates and FPGA2 with 4-input gates
(or anything like this difference). How do you code RTL for best
efficiency for both platforms ?

> Mind you the last nice RTL language I saw was for punched cards
> computer and output to FORTRAN as simulation. (A yellow book if
> I remember right with a title like  Register transfer language
> and simulation )
Damnit, i'll have to dust off my IBM 7080 :-P
what was the langage's name, btw ?

> Ben Franchuk - Dawn * 12/24 bit cpu *
WHYGEE
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