[f-cpu] non standard cell

[<nicolas.boulay@ifrance.com>]

hi again, again,

nicolas.boulay@ifrance.com wrote:
> -----Message d'origine-----
> De: Yann Guidon 
> A: f-cpu@seul.org
> Date: 12/02/02
> Objet: Re: [f-cpu] register set
> 
> hello,
> <..>
> By the way, if people are "eager" to have a D-ff,
> i could probably reuse the dual-edge flip-flop idea
> and adapt it a bit...
> ----
> >>>> Dual-edge ???? No, we will use normal cell
find
> in every technology and not a special thing that
> could only be manualy implemented.

once you have designed the dual-edge cell, you can
reuse it instead
of the standard cell. The problem might come from
static timing analysis
but the effect is that it will return an operating
frequency that is
2x that of the real frequeny.

You seem to like power consumption reduction :
dual-edga flip-flops
require almost as many room as a normal one, at least
with the sxlib
of Alliance. However, you can drop the clock tree's
frequency which
is likely to reduce the power consumption by 25%
(granted 50% of
the power is drawn from the clock and its frequency
is reduced by 50%).

>>>>> Only one compagny could create a new cells for
their technology, the one who maid it. If an other
compagny, want to create such new things it will pay
... a lot ! (because ST, IBM, UMC, TEMIC,... should
relance a complete series of teste before you could
used it !) 

Failling edge flipflop could be usefull to send data
to the outside of the chip, so with such thing it
will become much complicated.
Maybe if somebody create such flipflop we could use
it. We will see at that time !

> Please, think only on rising edge D-flipflop (or
RS).
i do that all the time. But dual-edge comes as a
replacement
cell which does not change the timing (just halve the
clock frequency).

> Even using falling
> edge flipflop is a very bad idea, some technology
> used a not gate before the clock entrance to
simulate
> the right beaviour.
"if the tool is broken..."

> For large "storage" area like register bank,
> memories,caches, TLB, ... we need to create
specific
> entites that could used specific macrobloc of the
> technology (internal memory in Xilinx, compiled
SRAM
> for semi-custom chip,...)

"show me the code" :-)

>>>> As you try to explain there is no "generic" SRAM
entites, that's why we need to create a fixed entites
and then fill it with technological dependant things
when we want to use it.(as does by leon for there
register bank)
But we need a "generic" pure VHDL synthetisable code,
that work but will be slow and big!  

I looked at LEON specifically for that, and it's
poorly explained.

>>>"Read the code." ;p

> nicO
WHYGEE

>>>>nicO

 
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