Re: Rep:Re: [f-cpu] register set, latches

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Kim Enkovaara wrote:
> I'm little lost, what is going to be the design methodology with FCPU for
> ASIC. Is it full manual layout and GDSII signoff or standard cell based
> technology and possibility for netlist signoffs. There is no way you can
> get your own cells to vendor libraries without big amounts of money (and
> timeframes are long for new cells). And how about dual-edge cells in FPGAs
> etc.

Lets not forget here that FPGA's could be quite useful as hardware
emulators of standard cell libraries. Until you start coding real
programs and building hardware even if it is 100x slower than the real
thing you will not be able to correct the architecture for unforeseen
problems. On my own FPGA cpu design I found I made 25% more changes
after I had a mostly working cpu to correct for logic bugs,
architectural improvements and added features, ( like a fast interrupt
for floppy disk or byte swaps ), or better ways of doing things. It is
only after your major 30'th revision do you get things right.:)
-- 
Ben Frantic - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
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