Re: test (was: Re: Rep:Re: Re: [f-cpu] No latches, please !)

[Kim Enkovaara <embo@mpoli.fi>]

> Concerning the test, remember that there is a BIST unit that
> takes control of the whole datapath and takes care to test
> all the execution units and the memory arrays. If the "latch"
> (those you like and/or those you don't) is in the datapath,
> it -will- be tested. Those that can't be tested without complex
> stuff will use a classical scanpath but the scan chain will be
> kept as short as possible.
> By the way, one of the optional units (popcount) will certainly
> be used for signature compaction.

How many patterns have you tought to use. Datapath style BIST takes very
long times, probably many days. Each second in ASIC tester costs real
money. You need very quick results in ASIC tster to notify if the chip is
OK (IDDQ tests, ATPG patterns, quick RAM bists etc.)

> How much do i have to emphasize on this ?
> Yes, this will be custom-designed test but
>  - we don't need ATPG
>  - we couldn't afford it anyway
>  - always trust your nose and make meaningful measurements.

I doubt that you can make the BIST to cover the whole chip without
sacrificin performance and the test times will be huge. Also "all" the
commercial Logic BIST testers work by hooking into the scan chains and
they generate patterns to those chains. Also to minimise the test time
Logic BIST needs quite complex things (reseedable pattern generators,
randomness distribution changes based on feedback, random generator
optimization based on scanpath and design etc.)

BIST is only a small part of testing. It is good for memories and
fullspeed logic testing but to get >95% coverage for logic with BIST is
very challenging.

--Kim

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