Re: [f-cpu] virtually or physically-addressed cache ?

["Marco Al" <marco@simplex.nl>]

From: "Yann Guidon" <whygee@f-cpu.org>
> Marco Al wrote:
> > From: "Christophe" <christophe.avoinne@laposte.net>
> > > Virtual or physical addressing ?
> > > -------------------------------------------
> > > (1) virtually-addressed caches (virtual tags)
> > >
> > > + do address translation only on a cache miss
> > > + faster for hits because no address translation
> >
> > Another plus to this method, its the only way to go with software
managed
> > address translation AFAICS.
>
> ?????
>
> Currently i plan and design a physically-addressed cache (2).
> It adds a translation cycle but i don't see any other problem.
> And since it is pipelined and the pipeline splits the operation
> (access and addressing), the TLB lookup is not inside the visible
> software latency (unless you program badly).

Sotfware managed address translation does not need to use a TLB as such (if
you think about it a bit you will see that thats possible, given the 2 first
plus's). I would think that would appeal to your minimalistic side :)

There will always be algorithms which can not avoid deep pointer chasing,
however well implemented. Im sure there are plenty of other realistic cases
where the latency of memory access even on cache hit can be a bottleneck,
numerical computations with nice straightforward structure is not exactly
something most desktop processors spend much time doing ...

Marco

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