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[f-cpu] VHDL and delay estimation



hello

still about float point adder...
I would like to have hint about delay estimation from VHDL source code since i cannot synthetise at home...
For exemple, how much this instruction cost (in gate deep):

if (EffSub = '1') then
My := not My;
grs := not grs;
end if;


and for:

if (ReprB (REPRES_NORMALISED) = '1') then
Mb(M_SIZE) := '1';
else
Mb(M_SIZE) := '0';
end if;
?



next one:
how much this function cost
procedure fpu_rshift(F : in std_ulogic_vector; N: in std_ulogic_vector;
G : in std_ulogic_vector;
Y : out std_ulogic_vector; B : out std_ulogic_vector;
s : out std_ulogic
) is
constant LF : natural := F'length;
constant LN : natural := N'length;
constant LY : natural := Y'length;
constant LB : natural := B'length;
constant LG : natural := G'length;
constant L : natural := LG+LF+LB;
variable gg : std_ulogic_vector(LG-1 downto 0) := G;
variable ff : std_ulogic_vector(LF-1 downto 0) := F;
variable yy : std_ulogic_vector(L-1 downto 0);
variable ss : std_ulogic;
constant default_bit : std_ulogic := '0';
begin
yy(L-1 downto LB) := gg(LG-1 downto 0) & ff(LF-1 downto 0);
yy(LB-1 downto 0) := (others => default_bit);
ss := '0';
for i in 0 to LN-1 loop
if (N(i) = '1') then
-- reduce_or need a vector with size 4.n
if i=0 then
ss := ss or yy(0);
elsif i=1 then
ss := ss or yy(0) or yy(1);
else
ss := ss or reduce_or(yy(2**i-1 downto 0));
end if;
yy(L-2**i-1 downto 0) := yy(L-1 downto 2**i);
yy(L-1 downto L-2**i) := (others => default_bit);
end if;
end loop;
Y := yy(LF+LB-1 downto LB);
B := yy(LB-1 downto 0);
end procedure

it's the right shifter (N is at max 6 bit sized)
it also the same thing as

if (N(0) = '1') then
yy(L-1) := G;
yy(L-2 downto 0) := F(L-1 downto 1);
else
yy := F;
end if;
if (N(1) = '1') then
yy(L-1) := G;
yy(L-2) := G;
yy(L-2-1 downto 0) := yy(L-1 downto 2);
end if;
if (N(2) = '1') then
yy(L-1 downto L-3-1) := (others => G);
yy(L-4-1 downto 0) := yy(L-1 downto 4);
end if;
if (N(3) = '1') then
yy(L-1 downto L-7-1) := (others => G);
yy(L-8-1 downto 0) := yy(L-1 downto 8);
end if;
if (N(4) = '1') then
yy(L-1 downto L-15-1) := (others => G);
yy(L-16-1 downto 0) := yy(L-1 downto 16);
end if;
if (N(5) = '1') then
yy(L-1 downto L-31-1) := (others => G);
yy(L-32-1 downto 0) := yy(L-1 downto 32);
end if;

The true question is: after these 3 steps (MSB, not and shift) do i have enought place to put a n-bit half adder (1xor deep)...????

Thanks to everyone helping me, a VHDL-synthesis newbie ;-)

--

~~ Gaetan ~~
http://www.xeberon.net


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