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[f-cpu] New Old Guy
Hi,
I'm back and still interested in the project. Where are the up-to-date materials hosted?
rares (you may find me as mechan0r in different places)
----- Original Message -----
From: Yann Guidon <whygee@f-cpu.org>
Date: Wed, 11 Feb 2004 04:13:29 +0100
To: f-cpu@seul.org
Subject: Re: [f-cpu] SIMD and exception
> hi,
>
> gaetan@xeberon.net wrote:
>
> > [...]
>
> sorry i can't follow everything ...
>
> > ok thank you very much. !!
> > If i count well, i'm far from 4 stages for fadder... it will take at
> > least takes 6 cycles... :'(
>
> i don't think that it's a rally critical issue.
> if it works correctly and can be deeply pipelined,
> it will be very valuable for the F-CPU, unlike
> other "off the shelf" IP cores.
>
> I have read small parts of Kahn's work
> (from the URL that you gave) and i have found
> interesting explanations : for example the
> progressive underflow managed by inserting
> pseudo-instructions in the pipeline, or detecting
> risks of underflow in advance with the MIPS method.
> That's really interesting.
>
> YG
>
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