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Re: [f-cpu] System C


> > We are developping some EDA tools to
> > support it, including a C++ class library that can be seen as 'the basis
> > of System C'. This is exactly the same philosophy: It enable integrated
> > HW/SW (co-)simulation with different refinement level (from data flow to
> > RTL) and it can also be used to generate synthetizable vhdl or verilog
> > code. The library is really stable (more than System C ;-) and has
> > already been used internally for several high-ends designs (inclusing a
> > cable-modem, a 802.11a-like (it was before the standard) baseband
> > transceiver, ...). You can have more information on
> > http://www.imec.be/desics/design_technology_top.html
> > It can be used freely even it is not really under GPL.
> We are already full-steam into VHDL coding.
> In fact the largest part of the work is dealing with
> low-level things.
> When i tried to make some C simulations, when i tried
> to analyse the scheduler, it appeared that C is not adapted
> to this task. Or maybe i wanted to write VHDL code in C.
> More generally, i do not believe that SystemC-like development
> is useful now because it's a low-level thing, mostly bit manipulations
> on a cycle by cycle basis on an already partitioned design.
> SystemC is mostly used for "SoC" where the designer must
> trade-off between HW and SW, but there is no SW needed here :-)
> It would be useful for a communication protocol analyser,
> for a MPEG/JPEG stream compressor/decompressor, for specific
> applications requiring some complex and heavy load where
> the HW optimisation must be balanced with the latency and costs.

That's true, and that's the kind of system I am used to cope with ... Anyway,
System-C or SysC-like libraries can also make your life easier when you try
to model and simulate a 'system' (it can be a CPU) which is not completely
refined. The idea is to start the design by discribing a 'data flow' model
(that sound DSP-like but it can be extented). The interest is that you can
model a collection of concurrent processes (exactly like in vhdl) that are
described in high level C. You don't need to be cycle-true at that level.
Then, you refined your model process by process (fixed-point quantization,
timed behavior ...) using the support of the library. The output is a FSMD
model that can be automatically translated into vdhl or verilog for
synthesis. At any time in the development, you can 'run' (simulate) the
complete system, even if it is not completely refined.

Now, this is 'our methodology', I don't say it is the best ...

> This is not the case with F-CPU.

I don't know it enough to judge fairly

> However it is certainly very interesting to learn from the
> newest design concepts and particularly from IMEC. Maybe F-CPU
> could find a place, not as a user but as component of new
> technologies ? Or at least there can be a way to cooperate
> on implementing a chip ...

Sure that I would like to have a look at your code. Do you have a cvs server


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