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I see some points made on
circuit loading. While at Sanders Associates Inc several years back; it
was determined that a Logic design having a maximum fan-out of 7 loads had a
good chance of surviving temperature testing over the military temperature range
of -55 to +125c. In my design of the Erin32 I took special care to have a
maximum load of 8. In the chip design process; there is an Auto-buffer
option - I always use it.
The End-item Processor is a
Quicklogic Corp QL6600-7 672 pin Plastic Ball Grid Array device of the Eclipse
Family. The current useage of the device is as follows:
Utilized cells (no buffers)
3048 of 4032
Utilized cells
(buffered) 3537
of 4032
Clock only
Cells
1 of 9
Bi
Directional cells 502
of 506
PLL cells
1
of 4X
Flip-flop of IO
cells 224
of 508
1st Flip-flop of Logic cells
981 of 4032
2nd Flip-flop of Logic
cells 982 of
4032
Routing
resources 83167
of 293995
ViaLink
resources 73301
of 7957982
Global Clock Nets
9
of 9
OSC1 Clock
93
MHz
This design is of the M2M
variety that you people are steering clear of. A modified Harvard
Architecture is used -
that is separate Program and Data memory also
having an 18 bit Source and Destination address, and ONE ACCUMULATOR
REGISTER. Eight (8) Instructions and eight (8) operands are fetched and
executed in parallel if Data Waits do not interfer. This function was also
shot down by you people - since I have used this feature some time ago (before
most of you were born); I used it again, instead of using Cache. To me it
appears that 8 instructions is a good number because one of eight is probably of
the Jump or Conditional variety anyway. This is borne out of the analysis
I did a couple years back - and the numbers are approximately
correct.
The design is all Schematic
Level, so I have complete visability of every GATE. Although the Two and Four
Port SSRAM's have an access time of 4.5 NS; I round this to 5, and 5 NS
setup, and 5 NS Ram to CPU I/O pin.
Multiply and Divide are
included; however Square Root had to be abanded due to an insufficient number of
Logic cells. This will require a separate optional Chip. This will fit very well
in the Optional Floating Point Processor.
I will be very happy to answer
any questions of the design.
Regards
Richard E. Hartney
Research Director
Erin Greene & Associates
E-mail rhartney@bellsouth.net
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