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[f-cpu] PS

Looks like we'll need a separate, low-latency and simple protocol for both interrupts and semaphores.
Something located in an independent address space (if any), with no caching quirks and which communicates
almost directly (but point-to-point) with other cores. That's not difficult to do but i have to make sure
this doesn't already exist. The VCI stuff is more important now because the memory interface must
be designed, the IRQ and semaphore machinery is to be designed a bit later.

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