Re: [f-cpu] statistics of direct indexing usage

[nico <nicolas.boulay@ifrance.com>]

On Tue, 7 Jan 2003 19:02:47 +0100 (CET)
devik <devik@cdi.cz> wrote:

> Hi,
> only quick result I just got. I tested with large source file
> (combine.c from gcc) and tried to see what if I add load/store
> with immediate offset to F-CPU ISA.
> Without imm:
> total insns: 29283
> Labels: 2058, JMP: 2568, Conditional jumps: 3034, loadaddr: 3543
> Simple L/S: 4881, post-update L/S: 618, imm-offsets:
> 
> And with 6bit offset (+- 32 words):
> total insns: 27307
> Labels: 2122, JMP: 2611, Conditional jumps: 3033, loadaddr: 3515
> Simple L/S: 2236, post-update L/S: 558, imm-offsets: 2594
> 

The question was more the comparaison with the 8 bits imm operand.
Because 8 bits use 2 flags bits, not all reg-reg operations could be
handle using 8 bits imm. So the question was what is the occurence of
this impossible 8 bits immediat instructions, and is it harmfull for
speed ?

> Also all postupdates can be converted to imms (I didn't it
> yet - they are in prolog/epilogs).
> You can see that about 70% of all load/stores are offsetted
> in this small range. Using it saved about 2000 instructions
> (9% in this file). I also expect higher speed because in
> original file you can see too many address "adds" tightly
> one after other.
> Even if +-32 bytes (not words) displacement it is:
> total insns: 27509
> Labels: 2111, JMP: 2606, Conditional jumps: 3033, loadaddr: 3512
> Simple L/S: 2511, post-update L/S: 561, imm-offsets: 2348
> 
> It is only about 10% worse than +-32 words imediate but still
> very good and resulting address is in range of up to two
> cachelines - so that it should not be so hard to implement it !
> 
> Your opinions ?
> 
> devik
> 
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