Re: [f-cpu] latest gcc & immediate addressing [Was: BOUNCE f-cpu@seul.org:...] (fwd)

[cedric <cedric.bail@free.fr>]

> Unfortunately, this is not always true: the ROP2 (logical) operations
> behave differently. They really suck when it comes to efficient non-SIMD
> code generation (in particular, conditional branches); we should talk
> about changing the ISA definition (without sacrificing the current
> functionality, of course). E.g. we could define the following variants:
>
>     // these are new
>     <op>.<and|or>.<size>    // truncates result to chunk size
>     <op>.<size>             // truncates result to chunk size
>     mux.<size>              // truncates result to chunk size
>
>     // these correspond to the current ones without `s' prefix
>     s<op>.<and|or>.<size>   // always operates on full register (size used
> for combine)
>     s<op>.<size>            // always operates on full register (size is
> ignored)
>     smux.<size>             // always operates on full register (size is
> ignored)
>
> Then your assumption would be valid again.

> > >     - logic operations take 9-bit signed immediate operands.
> >
> > uhh .. my 2.7 manual doesn't state it :( Where can I find it ?
>
> Dunno. I read it somewhere (maybe in the source code), and implemented
> it in both the assembler and the emulator.

Hum, I have a problem here, I don't find any empty room for that in our ISA. 
How did you implement it, by using some of the OP_CODE bits ?

Cedric
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