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Re: [f-cpu] statistics of direct indexing usage



hi !

devik wrote:

FC0 at 1GHz is science fiction for me.
However, a 2-way or 4-way FC0 system could probably do the same work.

:) sci-fi from technical or financial point of view ? I take
it from financial point - to get access to appropriate
technology. But is there anything what would prevent FC0
to go multi-GHz ?

From the little i know, the register set, as it is, is the main problem.
it's a huge piece of silicon and i count on FC1 (a highly hypothtical thing)
to solve this problem (among others). It's probably possible to adapt
FC0 to reach 1GHz, but it's probably not worth it. It's better to
target the design of the next architecture towards this barreer,
while the main goal of FC0 is 1) to work 2) to not look ridiculous
(and i guess that the first custom dies will be around 200MHz, which
is not bad, compared to other 64-bit computers of the same class
like embedded MIPS64 chips).

However, FC0 is not large compared to a recent x86 spearhead,
so it's possible to fit several ones on a chip, or make many for
the price of one. When you add to that a good SMP-capable kernel,
you can have a good computer with lower EMI and consumption problems :-)

I am now (among other things) trying to build a prototype, highly experimental
and non-serious 4-node computer with 4 Europe-sized 486-66 boards.
I also bought some EPLD and that should be enough to build a crossbar
on the ISA backplane (but there are a lot of potential problems, like clocks
and pin count etc).
i hope i can get some help from the L4/Hurd people for the microkernel
part of this silly project :-) Of course, the goal is to learn and develop things
that will be reinvested directly into F-CPU, in order to ease the design
of heterogeneous SMP systems.

YG

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