Re: [f-cpu] Instruction census

[Michael Riepe <michael@stud.uni-hannover.de>]

On Tue, Jan 14, 2003 at 10:18:59PM +0100, devik wrote:
[...]
> > > well, mac is not yet supported - we have generaly problems
> > > with ^1 register addressing.
> > >
> > What kind of problem ?
> 
> MR explained me that MAC doesn't have that problem. But
> MUX has - there is no clean way to tell gcc that insn
> places result to register r^1 ...

In the emulator, I don't do that (result goes into r1, as with mac).
The alternate register is only used when an instruction returns two
values (like mulh, divrem, (f)addsub, dshift, sort and so on).

> It can be done for divrem because it uses expander. But
> MUX will gave to be solved by 3-2 split point of gcc only
> because it consists of 3 RTL insns.

You could write an expander for `ior' that checks the arguments and
generates a `mux' if it finds the special case.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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