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[f-cpu] 4w1r register file
- To: <f-cpu@seul.org>
- Subject: [f-cpu] 4w1r register file
- From: devik <devik@cdi.cz>
- Date: Wed, 15 Jan 2003 13:44:24 +0100 (CET)
- Delivered-to: archiver@seul.org
- Delivered-to: f-cpu-outgoing@seul.org
- Delivered-to: f-cpu@seul.org
- Delivery-date: Wed, 15 Jan 2003 09:02:42 -0500
- Reply-to: f-cpu@seul.org
- Sender: owner-f-cpu@seul.org
Hi,
please I I'd need 4w1r (8w1r) file with 4 registers,
how complex is it ?
I'd do one bit as (sel0 & w0)|(sel1 & w1)|...(selN & Q)
in D input of FF. I know selX values ahead ..
It seems as 1 2port ANDs followed by 5 or 9 port OR
and then FF.
I'm wondering whether such regfile write port would
be within 6gates and allow multi-GHz clocking .. :-)
devik
PS: for curious, I just got idea for simple and
interesting 4/8 way superscalar design ..
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