Re: [f-cpu] Instruction census

[devik <devik@cdi.cz>]

> > MUX has - there is no clean way to tell gcc that insn
> > places result to register r^1 ...
>
> In the emulator, I don't do that (result goes into r1, as with mac).
> The alternate register is only used when an instruction returns two
> values (like mulh, divrem, (f)addsub, dshift, sort and so on).

good news.

> > It can be done for divrem because it uses expander. But
> > MUX will gave to be solved by 3-2 split point of gcc only
> > because it consists of 3 RTL insns.
>
> You could write an expander for `ior' that checks the arguments and
> generates a `mux' if it finds the special case.

hmm ior is handed with constants or registers or memory
to expander. There is no "legal and realiable" way to see
its arguments ...
But splitter does the job for this concrete one. For others
I'd really like combine.c to be able to have hook in insn
to specify actions to do after combiner matched pair.
Then we could inject (subreg:DI (reg:TI) 8) to address r+1
register...

devik

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