[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Instruction census



On Wed, 15 Jan 2003 10:37:32 +0100 (CET)
devik <devik@cdi.cz> wrote:

<...>
> > > BTW what is load-linked/store-conditional ?
> > I don't think so or by an other chip maker.
> 
> you misunderstood the question, I asked WHAT is
> load-linked/store-conditional .. I don't know the name.
> 

It's a technic to "simulate" read-modify-write on a monocpu computer. It
work like you're ld.a ld.s. but the second instruction is a store. The
store failed if the adresse is changed or if a trap occure or something
like that.


> devik
> 
> *************************************************************
> To unsubscribe, send an e-mail to majordomo@seul.org with
> unsubscribe f-cpu       in the body. http://f-cpu.seul.org/
> 
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/