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HI GUYS
Still looking and
watching. I am using 39, yes I said 39 ALP76 Processors which serve as my
Language Processor. The TIPS Software that I am capturing is written in
re-locatable code. None of the routines are more than 512
Instructions. Each Processor is assigned a specific Block and forwarding
is accomplished via Interrupt to select a Specific Sub-routine (processor).
No processor services more than eight (8) subroutines. To prevent a
logjam multiple processors are used.
The TIPS software can be used
almost as is. I didn't plan it that way, but that is the way the cookie
crumbled; so to speak. In addition; I am on using the ON-CHIP
RAM for Instructions and Operands. In some cases
the Operand is OFF-CHIP and
Arbitration is required for Reads and Writes to the
SSRAM four port things. These are organized horizontally in a group of
eight where each has a dedicated Read and Write Port so the arbitration is to
one of the eight. I think I say that correctly.
Questions will certainly be
replied to.
Regards
Dick Hartney
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