Re: [f-cpu] Another simulator!

[Yann Guidon <whygee@f-cpu.org>]

hi,

nico wrote:

> On Fri, 24 Jan 2003 04:40:03 +0100
> Michael Riepe <michael@stud.uni-hannover.de> wrote:
>
> > On Thu, Jan 23, 2003 at 05:41:20PM +0100, Yann Guidon wrote:
> > [...]
> >    
> > > Note that in order to be both attractive and efficiently coded,
> > > one has to take ultra-wide register sizes from the start.
> > >      
> > [...]
> >
> > I tried to, but I don't know if I got everything right.  E.g. will
> > special registers grow as well?  What does loadaddr calculate when
> > general registers are wider than 64 bits?  Will loadconsx really
> > sign-extend to the full register size, or only to 64 bits?  Will `jmp
> > r1, r2' ignore the
> >    
> > From the beginning of the story, register could grow but the size of the
> manipulated date stay at 64 bits. It's only for SIMD stuff (256=4*64).
>
> So there is no real question from my point of view.
>
> nicO
>  
I know that a lot of details must be examined, but it is also clear for me
that SRs have the same size as normal registers. Otherwise it cuts
all the extensibility and orthogonality of the architecture.

Basicly, SRs are accessed with GET and PUT, with no size parameter,
this means that the whole register is written or read from/to the 
designated SR.
For me, 64-bit data are only a "base size" or a "least common denominator".

YG

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