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[f-cpu] Prefetcher (instruction cache L0) our first draft
- To: f-cpu@seul.org
- Subject: [f-cpu] Prefetcher (instruction cache L0) our first draft
- From: Pierre Tardy <tardyp@free.fr>
- Date: Mon, 12 Jan 2004 16:35:06 +0100
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- Delivered-to: f-cpu@seul.org
- Delivery-date: Mon, 12 Jan 2004 10:35:31 -0500
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- Sender: owner-f-cpu@seul.org
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Attached the modifications of fctools0.3's emu, by tired.
We have added an instruction cache L0. As it is not well defined in the
handbook, we are requesting comments about this code.
The algorithm is well explained as comments in the code (prefetcher.c)
We have an asm code that do matrix multiplication ( with 3 embraced loops).
We are also requesting comments about this code, and our understanding of the
f-cpu way of coding.
greets,
Pierre and François.
Attachment:
emu.tgz
Description: Binary data